Description

EMCCD (Electronic Multiplication CCD) is a new type of solid-state imaging sensor. Owing to the unique feature of on-chip multiplication. EMCCD obtains the same level of sensitivity compared with ICCD and EBCCD, Back Illuminated EMCCD-EMBCCD further enhanced the sensitivity. In addition, based on the standard CCD fabrication techniques, EMCCD also features high quantum efficiency. Due to these advantages, EMCCD has various applications on astronomy, aerospace, life science and military. This paper has implemented an imaging system circuit design based on EMBCCD.

This paper first described the operating mechanism, main characteristics of CCD and EMCCD. Based on the datasheet of EMBCCD-CCD97, FPGA was utilized to generate the timing sequence of EMBCCD; In order to better meet the EMBCCD driving specification, the exist driving circuit was substituted by a specialized CMOS driver IC and a separate high voltage driving circuit for level shifting; The EMBCCD output analog signal was sampled and converted to digital signal by a CCD signal processor; The converted CCD digital data was transmitted to FPGA, cached in SDRAM and finally displayed on a VGA monitor.

Publications

Dengyu Liu and Guangrong Liu. EMBCCD Driver, Signal Pre-Processing and Image Acquisition Circuit Design(in Chinese). Master Thesis. Beijing Institute of Technology, Beijing 2010

Images

	Frame Transfer CCD Architecture: Frame transfer CCD architecture contains mainly four parts: image array, storage array, serial register, output amplifier. When exposure is on, light from the image is projected onto the image array. Collected photons are transformed into electrons in each pixel. After integrating a scene, electrons are shifted into storage array, which is non-sensitive to light, via the control of parallel clocks. While integration is undertaking in image array, the previous collected electrons in storage array are transferred row-by-row to seiral register, and finally sent to output amplifer with the driving of serial clocks. Electrons are converted to voltage after the output amplifier. (figure from Kodak
	EMCCD Structure: Electronic Multiplying CCD(EMCCD) is similar to traditional frame transfer CCD. The difference is that EMCCD features an on-clip multiplication stage. The additional multiplication register R2HV allows weak signals to be multiplied before any readout noise is added by the output amplifier, hence rendering the read noise negligible. The register has several hundred stages that use higher than normal clock voltages. As charge is transferred through each stage the phenomenon of Impact Ionization is utilized to produce secondary electrons, and hence EM gain. When this is done over several hundred stages, the resultant gain can be (software) controlled from unity to hundreds or even thousands of times. (Figures from E2V and www.EMCCD.com)
	High Voltage Power Driving Circuit: In order to generate a high speed(10MHz), high magnitude(40v) driving pulse, we build a push-pull amplifier using two complemetary sysmetry transistors. 74HC04 is located in the input statge to increase the load capacity. High speed Schottky barrier diode are used to clamp, avoiding transistor entering deep saturation state.
	EMCCD Control Timing Driven by FSM: In order to drive EMCCD, we need to follow its control timing. We utilize Finite State Machine(FSM) to generate the timing. By dividing the timing into several stages, with specified voltage level assigned for each pin in each stage, the whole timing can be generated using verilog HDL.
	Simulation of EMCCD Control Timing: The EMCCD control timing is designed using verilog HDL driven by a finite state machine. Simulation is implemented in Model Sim. The whole timing, zoom on frame transfer stage and line transfer stage are shown.
	Block Diagram of System Timing Design: 50MHz clock oscillator generate the base clock signal, which then passes througth PLL to generate clock signal for CCD driver, SDRAM read/write and VGA control. The CCD driver & AD sampling module is used to drive EMCCD and also control CCD image processing chip. SDRAM buffer module is used to buffer image data into external SDRAM via the control of FPGA. Finally, VGA controller module is used to read out image data from SDRAM and sent it to VGA control chip for display.

Slides

Master Thesis Presentation(in Chinese)