CID Theory

Pixel Structure of a CID Pixel

The pixel layout of CID is shown in Figure 1. The pixel is front illuminated since there is only a small amount of gating structure on the top surface to obstruct incoming photons. A thin metal strip is put on top of the row polysilicon to reduce the readout noise. The drawback to this opaque structure is a small amount of obstruction of the incoming light. Each pixel consists of a pair of orthogonal polysilicon electrodes which create two MOS capacitors in n-doped silicon for storage and sensing of photogenerated charge. These electrodes also connect the rest of the pixels on the column or row to the scanners on the periphery.

Figure 1.

Integration of photogenerated holes occurs in the positively biased epitaxial region. Since the substrate is grounded, a reverse biased p-n junction is created inside of every pixel. This provides excellent antiblooming protection when overexposed since excess holes outside the well are swept through the p-n junction to the substrate. Negative or slightly positive voltages on the column and row electrodes create depletion wells for storage of holes.

Array Layout of a CID

In preamp per row (PPR) devices such as shown in Figure 2, columns are biased more negatively and holes collect under this electrode called the "collection pad". All pixels along a particular row are amplified by the same FET and hence the PPR architecture requires slight calibration of the 512 row FETs to minimize nonuniformities between them. Further reduction of read noise can be achieved with preamp per pixel (PPP) structures currently being manufactured by CIDTEC.

Figure 2.


Two types of readout techniques are shown in Figure 3. During readout, a "zero level" is captured on the sense pad along the row by allowing the pad to float and digitizing. The sole charge transfer from the collection well to the sense well is performed by driving the column high and all stored charge moves to the sense well. The amount of collected charge sensed on the row electrode modulates the drain-source current of the output FET amplifier. In non-destructive readout (NDRO) the low potential on the collection pad is reestablished and accumulation continues. In destructive readout (DRO), the pixel is injected.

Figure 3.

A subarray of pixels are read along a row by shifting the column register until the all of the pixels have been read. The column register is then reset and the row register shifted to the next row. This row read operation is repeated for all of the rows. This method of readout differs from "true" random access. Any single CID pixel can be randomly read but the addressing of that pixel is achieved by quickly shifting through row and column shift registers to get to the pixel. A true random access array with multiplexing, the CID-810, is under development and will be tested soon.

Injection Methods

Pixel injection can be performed with two different methods. The entire array can be cleared in one step with "global" injection. This is done by simultaneously driving all columns and rows to Vinj, the prescribed injection voltage. Each pixel in the array then has both pads biased such that holes are injected into the substrate. The other injection method removes only the charge in a subarray in a method similar to array readout. In "subarray" injection, each pixel is addressed sequentially as during readout and the injection voltage is applied to the row electrode. Horizontal shifting during subarray injection (0.2mm/pixel) is substantially faster than readout (62mm/pixel).

The commercial electronics, or SiCam, generates the readout and injection clocking sequences with a sensor control board . These clocks drive the shift registers on the periphery of the CID and produce the pixel readout and injection results described above.